Impact of the CNT Parameter Variations on Performance of Digital Circuits Based on CNTFET

Document Type : Research Paper

Authors

1 Institute of Intelligent Industrial Technologies and Systems for Advanced Manufacturing (STIIMA), National Research Council of Italy, 70125, Bari, Italy

2 Electronic Devices Laboratory, Department of Electrical and Information Engineering, Polytechnic University of Bari, 70126, Bari, Italy

Abstract

   In this paper we propose a method to study the impact of the CNT parameter variations on performance of CNTFET digital circuits. In particular we consider CNT parameters that fully identify the geometrical properties of a regular CNT, which are the length and structural indices (n, m) of CNT. We analyse in particular the effects on NAND gate using a N and P type CNTFET, polarizing at a fixed voltage and varying the CNT parameters.  As regards the indices, we limit the analysis to zig-zag CNT, highlighting that the proposed procedure can be applied to other types of CNT.

Keywords

Main Subjects


  1. Marani, R., Perri, A. G., “CNTFET Modelling for Electronic Circuit Design”, ElectroChemical Transactions, 23 (2009) 429 - 437.
  2. Gelao, G., Marani, R., Diana, R., Perri, A. G., “A Semi-Empirical SPICE Model for n-type Conventional CNTFETs”, IEEE Transactions on Nanotechnology, 10 (2011) 506-512.
  3. Marani, R., Perri, A. G., “A Compact, Semi-empirical Model of Carbon Nanotube Field Effect Transistors oriented to Simulation Software”, Current Nanoscience, 7 (2011) 245-253.
  4. Marani, R., Perri, A. G., “A DC Model of Carbon Nanotube Field Effect Transistor for CAD Applications”, International Journal of Electronics, 99 (2012) 427 - 444.
  5. Marani, R., Gelao, G., Perri, A. G., “Comparison of ABM SPICE library with Verilog-A for Compact CNTFET model implementation”, Current Nanoscience, 8 (2012) 556-565.
  6. Marani, R., Gelao, G., Perri, A. G., “Modelling of Carbon Nanotube Field Effect Transistors oriented to SPICE software for A/D circuit design”, Microelectronics Journal, 44 (2013) 33-39.
  7. Marani, R., Perri, A.G., “Modelling of CNTFETs for Computer Aided Design of A/D Electronic Circuits”, Current Nanoscience, 10 (2014) 326-333.
  8. Gelao, G., Marani, R., Pizzulli, L., Perri, A. G., “A Model to Improve Analysis of CNTFET Logic Gates in Verilog-A-Part I: Static Analysis”, Current Nanoscience, 11 (2015) 515-526.
  9. Gelao, G., Marani, R., Pizzulli, L., Perri, A. G., “A Model to Improve Analysis of CNTFET Logic Gates in Verilog-A-Part II: Dynamic Analysis”, Current Nanoscience, 11 (2015) 770-783.
  10. Marani, R., Perri, A. G., “Analysis of CNTFETs Operating in SubThreshold Region for Low Power Digital Applications”, ECS Journal of Solid State Science and Technology, 5 (2016) M1-M4.
  11. Marani, R., Perri, A. G., “A De-Embedding Procedure to Determine the Equivalent Circuit Parameters of RF CNTFETs”, ECS Journal of Solid State Science and Technology, 5 (2016) M31-M34.
  12. Marani, R., Perri, A. G., “A Simulation Study of Analogue and Logic Circuits with CNTFETs”, ECS Journal of Solid State Science and Technology, 5 (2016) M38-M43.
  13. Marani, R., Perri, A. G., “A Comparison of CNTFET Models through the Design of a SRAM Cell”, ECS Journal of Solid State Science and Technology, 5 (2016) M118-M126.
  14. Marani, R., Gelao, G., Perri, A. G., “A Compact Noise Model for C-CNTFETs”, ECS Journal of Solid State Science and Technology, 6 (2017) M118-126.
  15. Marani, R., Perri, A. G., “CNTFET-based Design of Current Mirror in Comparison with MOS Technology”, ECS Journal of Solid State Science and Technology, 6 (2017) M60-M68.
  16. Gelao, G., Marani, R., Perri, A. G., “Effects of Temperature in CNTFET-Based Design of Analog Circuits”, ECS Journal of Solid State Science and Technology, 7 (2018) M16-M21.
  17. Gelao, G., Marani, R., Perri, A. G., “Effects of Temperature in CNTFET-Based Design of Digital Circuits”, ECS Journal of Solid State Science and Technology, 7 (2018) M41-M48.
  18. Gelao, G., Marani, R., Perri, A. G., “Effects of Temperature on Switching Time and Power Dissipation of CNTFET-Based Digital Circuits”, ECS Journal of Solid State Science and Technology, 7 (2018) M63-M68.
  19. Marani, R., Perri, A. G., “Design and Simulation Study of Full Adder Circuit Based on CNTFET and CMOS Technology by ADS”, ECS Journal of Solid State Science and Technology, 7 (2018) M108-M122.
  20. Marani, R., Perri, A. G., “Static Simulation of CNTFET-based Digital Circuits”, International Journal of Nanoscience and Nanotechnology, 14 (2018) 121-131.
  21. Marani, R., Perri, A. G., “Dynamic Simulation of CNTFET-based Digital Circuits”, International Journal of Nanoscience and Nanotechnology, 14 (2018) 277-288.
  22. Marani, R., Perri, A. G., “A Review on the Study of Temperature Effects in the Design of A/D Circuits based on CNTFET”, Current Nanoscience, 15 (2019) 471-480.
  23. Marani, R., Perri, A. G., “A Comparison of CNTFET and CMOS technology through the Design of a SRAM Cell”, ECS Journal of Solid State Science and Technology, 8 (2019) M1-M18.
  24. Gelao, G., Marani, R., Perri, A. G., “A Formula to Determine Energy Band Gap in Semiconducting Carbon Nanotubes”, ECS Journal of Solid State Science and Technology, 8 (2019) M19-M21.
  25. Marani, R., Perri, A. G., “A Design Technique of CNTFET-Based Ternary Logic Gates in Verilog-A”, ECS Journal of Solid State Science and Technology, 8 (2019) M45-M52.
  26. Gelao, G., Marani, R., Perri, A. G., “Three-Levels Logic Gates Design Based on CNTFETs”, ECS Journal of Solid State Science and Technology, 8 (2019) M67-M70.
  27. Marani, R., Perri, A. G., “Design of CNTFETs Operating in High Speed Sub-Threshold Condition for Ultra-Low Power Applications”, ECS Journal of Solid State Science and Technology, 8 (2019) M93-M101.
  28. Marani, R., Perri, A. G., “Effects of Parasitic Elements of Interconnection Lines in CNT Embedded Integrated Circuits”, ECS Journal of Solid State Science and Technology, 9 (2020) 021004.
  29. Marani, R., Perri, A. G., “Techniques to improve the Performance in the CNTFET-based Analogue Circuit Design”, ECS Journal of Solid State Science and Technology, 9 (2020) 031001.
  30. Marani, R., Perri, A. G., “Impact of Technology on CNTFET-Based Circuits Performance”. ECS Journal of Solid State Science and Technology, 9 (2020)
  31. Marani, R., Perri, A. G., “Temperature Dependence of I-V Characteristics in CNTFET Models: A Comparison ”, International Journal of Nanoscience and Nanotechnology, 17 (2021) 33-39.
  32. Marani, R., Perri, A. G., “Comparative analysis of noise in current mirror circuits based on CNTFET and MOS Devices”, International Journal of Nanoscience and Nanotechnology, 17 (2021) 121-129.
  33. Gelao, G., Marani, R., Perri, A. G., “Analysis of Limits of CNTFET Devices through the Design of a Differential Amplifier”, ECS Journal of Solid State Science and Technology, 10 (2021) 061009.
  34. Marani, R., Perri, A. G., “Study of CNTFETs as Memory Devices”, ECS Journal of Solid State Science and Technology, 11 (2022) 031001.
  35. Marani, R., Perri, A. G., “Analysis of Noise in Current Mirror Circuits Based on CNTFET and MOSFET”, ECS Journal of Solid State Science and Technology, 11 (2022) 031006.
  36. Marani, R., Perri, A. G., “Design of a Novel Full Adder Circuit based on CNTFET Technology”, ECS Journal of Solid State Science and Technology, 11 (2022) 051004.
  37. Marani, R., Perri, A. G., “Design and Characterization of Digital Gates based on CNTFET and CMOS Technology”, ECS Journal of Solid State Science and Technology, 11 (2022) 071004.
  38. Gelao, G., Marani, R., Perri, A. G., “Study of Power Gain Capability of CNTFET Power Amplifier in THz Frequency Range”, ECS Journal of Solid State Science and Technology, 11 (2022) 081005.
  39. Marani, R., Perri, A. G., “Noise Effects in the Design of Digital Circuits based on CNTFET”, ECS Journal of Solid State Science and Technology, 11 (2022) 111006.
  40. Marani, R., Perri, A. G., “Noise Effects in the Design of Analog Circuits based on CNTFET”, ECS Journal of Solid State Science and Technology, 11 (2022) 121010.
  41. Gelao, G., Marani, R., Perri, A. G., “Effect of CNT Parameter Variations on CNTFET Amplifier Performance”, ECS Journal of Solid State Science and Technology, 12 (2023) 011004.
  42. Marani, R., Perri, A. G., “A Technique, Based on Thevenin Equivalent Method, to Study the Noise Performance of Analog Circuits Involving both CNTFET and MOS Devices”, International Journal of Nanoscience and Nanotechnology, 19 (2023) 9-19.
  43. Marani, R., Perri, A. G., “Review—Simulation of A/D Circuits Based on CNTFETs both in SPICE and Verilog-A”, ECS Journal of Solid State Science and Technology, 12 (2023) 031002.
  44. Marani, R., Perri, A. G., “Critical Analysis of CNTFET-Based Electronic Circuits Design”, ECS Journal of Solid State Science and Technology, 12 (2023) 051005.
  45. Marani, R., Perri, A. G., “A Review on Static and Dynamic Characterization of Digital Circuits in CNTFET and CMOS Technology”, International Journal of Nanoscience and Nanotechnology, 19 (2023) 97-108.
  46. Shreya, S., Chandel, R., “Performance analysis of CNTFET based digital logic circuits". 2014 Students Conference on Engineering and Systems, Allahabad, India, (2014) 1-6.
  47. Lakhanpal, A., Sandha, K. S., “Impact of channel parameters on threshold voltage at variable temperatures of Double-gate CNTFET”, Micro and Nanostructures, 164, (2022), 107168.
  48. Tripathi, S. K., “Effect of CNTs Parameter Variation on the Performance of Analog Device”, International Journal of Recent Technology and Engineering, 9 (2020) 237-241.
  49. Verilog-AMS language reference manual, Version 2.2, (2014).
  50. Raychowdhury, A., Mukhopadhyay, S., Roy, K., “A circuit-compatible model of ballistic carbon nanotube field-effect transistors”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23 (2004) 1411-1420.
  51. Pregaldiny, F., Lallement, C., Kammerer, J. B., “Design-oriented compact models for CNTFETs”, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006., Tunis, Tunisia, (2006) 34-39.
  52. Prégaldiny, F., Lallement, C., Diange, B., Sallese, M., Krummenacher, M., Compact Modeling of Emerging Technologies with VHDL-AMS. Huss SA, editor, Advances in Design and Specification Languages for Embedded Systems, Dordrecht: Springer Netherlands, ISBN: 978-1-4020-6147-9, (2007).
  53. Datta S., Cambridge Studies in Semiconductor Physics and Microelectronic Engineering 3. Electronic Transport in Mesoscopic Systems, New York: Cambridge University Press, Online ISBN: 978051180577, (1995).
  54. Avouris, P., Chen, Z., Perebeinos, V., “Carbon Based Electronics”, Nature Nanotechology, 2 (2007) 605-615.
  55. Javey, A. et al., “High-kappa dielectrics for advanced carbon-nanotube transistors and logic gates”, Nature Mater, 1 (2002) 241-246.
  56. Deng, J., Wong, H.-S. P., “A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region”, .IEEE Transactions on Electron Devices, 54 (2007) 3186-3194.
  57. Deng, J., Wong, H.-S. P., “A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking”, IEEE Transactions on Electron Devices, 54 (2007) 3195-3205.
  58. Lee, C-S., Pop, E., Franklin, A.D., Haensch, W., Wong, H.-S. P., “A Compact Virtual-Source Model for CarbonNanotube FETs in the Sub-10-nmRegime—Part I: Intrinsic Elements”, IEEE Transactions on Electron Devices, 62 (2015) 3061-3069.
  59. Lee, C-S., Pop, E., Franklin, A.D., Haensch, W., Wong, H.-S. P., “A Compact Virtual-Source Model for CarbonNanotube FETs in the Sub-10-nm Regime—Part II: Extrinsic Elements, Performance Assessment,and Design Optimization”, IEEE Transactions on Electron Devices, 62 (2015) 3070-3078.